1. Field of the Invention
The present invention relates to a circuit for generating a clock signal which determines time points at which a color video signal is periodically sampled to be converted from analog to digital form by a digital-to-analog converter. More specifically, the invention relates to a circuit for generating such a clock signal, which is locked to a specific predetermined phase of the color burst signal component of the color video signal.
2. Description of the Related Art
Digital VTRs (video tape recorders) are coming into increasing use, in a variety of fields of application. Generally speaking, in the case of digital VTRs used in industrial applications, the composite color video signal is directly converted from analog to digital form prior to recording, without separating the luminance and chrominance components of the video signal for separate processing. In addition, to maximize the efficiency of utilization of recording tape, the horizontal and vertical blanking intervals (together with the synchronizing signals and color burst signal contained in these) are eliminated prior to recording the digital color video signal. In a color video signal, the chrominance signal is formed by combining two independently modulated signals (I and Q signals) each having an identical subcarrier frequency (i.e. 3.58 MHz, in the case of the NTSC television standard) and differing in phase by 90.degree.. Once in each horizontal scanning interval of a composite color video signal, a color burst signal occurs shortly after the horizontal synchronizing pulse (having a phase that differs from the I and Q phase values by fixed amounts) within the horizontal blanking interval. A television receiver which receives that color video signal (or receives a playback color video signal from a video tape recorder) contains an automatic phase and frequency control circuit which generates a reference chrominance subcarrier signal that is phase-locked to the color burst signal, and the chrominance signal is demodulated by using that reference chrominance subcarrier signal.
However in the case of an industrial-use type of digital VTR, in which the horizontal blanking intervals of the color video signal have been eliminated prior to recording, there will be no color burst signal present in the playback digital color video signal, for use in generating a local reference chrominance subcarrier for demodulating the chrominance signal. That problem is overcome by establishing a fixed relationship between the phase of the sampling time points used in the analog-to-digital conversion processing by which the analog color video signal is converted to a digital signal prior to recording, and a specific phase of the color burst signal. A local reference chrominance subcarrier can thereby be generated at the time of playback, based on the phase of the sampling time points, which can be derived from the playback digital color video signal.
Since the frequency of a sampling clock signal which determines the sampling time points used in analog-to-digital conversion will of course be equal to the chrominance subcarrier frequency multiplied by a factor that is greater than one, the term "fixed relationship to a specific phase of the color burst signal" or "locked to a specific phase of the color burst signal" signifies, assuming that the sampling frequency is four times the chrominance subcarrier frequency, that for example the sampling time points will respectively coincide with the 0.degree., 90.degree., 180.degree., and 270.degree. phase values of the color burst signal. Alternatively, with thae standard that is specified for D-2 format industrial-use digital VTRs, these sampling time points will be locked in phase to the I and Q components of the chrominance signal.
In order to accurately demodulate the chrominance signal by such a method, it is necessary to maintain a high degree of accuracy for the phase lock relationship between the analog-to-digital conversion sampling phase and color burst signal phase, i.e. the analog-to-digital conversion clock signal phase must be held accurately locked to within less than 2.degree. of error.
FIG. 1 is a a block diagram showing the basic configuration of a prior art circuit for executing analog-to-digital conversion using a sampling clock signal that is locked to a specific phase of a color video signal. In FIG. 3, numeral 1 denotes an input terminal to which is applied the color video signal that is to be subjected to analog-to-digital conversion, 2 denotes a digital data output terminal, 3 denotes an amplifier, 4 denotes an A/D converter, 5 denotes a color burst signal detection circuit, 6 denotes an adjustable phase shift circuit, 6a denotes a phase shift amount variation device such as a variable resistor, which is manually operable to alter an amount of phase shift that is produced by the adjustable phase shift circuit 6, and 7 denotes a phase locked loop (hereinafter referred to as a PLL). The analog color video signal that is supplied to the input terminal 1 is amplified by the amplifier 3 and then supplied to the A/D converter 4 and also to the color burst detection circuit 5. The color burst detection circuit extracts the color burst signal which is present in the back porch portion of each horizontal blanking flyback interval of the color video signal, i.e. once in each horizontal scanning line of that signal. The separated color burst signal is supplied to the phase adjustment circuit 6. At the time of manufacture, the amount of phase shift that is applied to the separated color burst signal by the phase adjustment circuit 6 is adjusted by an arbitrary amount, through manual adjustment by an operator of the variation device 6a. The phase-shifted color burst signal is then supplied to the PLL 7, which produces an output signal which is locked in phase with that color burst signal and is higher in frequency, and which serves as the sampling clock signal of the A/D converter 4. A predetermined phase relationship can thereby be established between that sampling clock signal and the color burst signal within the color video signal that is converted to digital form by the A/D converter 4. To establish that predetermined phase relationship, it is necessary for the operator to adjust the device 6a while PG,7 continuously observing a measurement apparatus (not shown in the drawing) that is coupled to the circuit shown in FIG. 1, and which enables the operator to ascertain when the predetermined phase relationship has been reached.
However with the such a prior art circuit for generating a clock signal which is locked to a specific phase of a color burst signal, since the phase adjustment must be carried out by manually executed operations, the adjustment process is time-consuming and will result in increased manufacturing cost, while the accuracy of phase adjustment may not be satisfactory. In addition, even if such a phase adjustment operation were to be automated at the stage of manufacture of digital VTRs, it may be subsequently necessary to readjust the phase relationship after a length of time has elapsed, since the phase of the sampling clock signal will be affected by changes which occur with time in the elements of the adjustment circuit and in peripheral circuits. For example the phase will be affected by variations in respective amounts of delay produced by circuit components which are positioned before or after the A/D converter, such as a low-pass filter, AGC circuit, clamp circuit, etc, or changes in delay produced within the A/D converter 4 itself.
For these reasons, it has not been possible in the prior art to provide a circuit for generating a clock signal for use in analog-to-digital conversion of a color video signal, which is locked to a specific phase of a color burst signal, and which will be free from the need to execute phase adjustments.